In modern semiconductor applications, populously packed transistors occupy a single wafer. To operate, the individual transistor components require electrical isolation. As such, many individuals, corporations and businesses have developed and continually strive for new techniques to achieve isolation. One popular recent technique, known as trench isolation, forms trenches or openings between adjacent components.
Commonly, depending upon application, trench isolation falls into one of three processing categories: shallow (or shallow trench isolation, STI), with trenches less than about one micron deep; moderate, with trenches from about one to about three microns; and deep, with trenches greater than about three microns.
In a typical trench isolation process to form a standard isolation structure, a wafer is provided with successively deposited dielectric layers thereon, usually a pad oxide and a nitride layer. The dielectrics are etched first and then the wafer. This results in a trench. A liner oxide for the trench is grown and the trench is oxide filled, usually by chemical vapor deposition (CVD). The oxide may be annealed and the entire structure is planarized, usually by chemical mechanical polishing (CMP). Then, the dielectric layers are removed by wet etch and a thin, sacrificial layer of oxide is grown to anneal wafer surface damage. This is followed by another wet etch. The gate oxide is grown, poly deposited and gate patterned.
Until recently, however, the foregoing techniques were sufficient for many applications. But with a device such as a dynamic random access memory (DRAM) array with sub-quarter micron dimensions requiring multitudes of highly-densely integrated, extremely low power transistors, even the slightest amount of transistor leakage may cause retention time failures in memory cells. As such, the state of the art, especially DRAM's, demand more robust isolation structures that completely prevent or greatly reduce undesirable transistor leakage.